Shift Register

ABSTRACT

A shift register comprises many stages, and each of stages comprises a first, a second and a third level control unit and a first and a second control unit is provided. The first and the second level control unit respectively provides a first clock signal and a voltage to an output terminal. The first driving unit and the level control unit are coupled to a first node. The first driving unit turns on and turns off the first level control unit in response to an input signal, a second control signal and a first control signal of the next stage. The second driving unit turns on and turns off the second level control unit in response to the first control signal. The third level control unit provides a first voltage to the output terminal in response to the second control signal and the first control signal.

The present application is a divisional of U.S. application Ser. No.12/275,455, filed Nov. 21, 2008, which claims the benefit of Taiwanapplication Serial No. 96144169, filed Nov. 21, 2007, the subject matterof which is incorporated herein by reference

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates in general to a shift register, and moreparticularly to a shift register used in a double-sided scan driver.

2. Description of the Related Art

With the rapid advance in science and technology, liquid crystal display(LCD) has been widely used in the displays of electronic products suchas TV, computer, notebook computer, mobile phone, personal digitalassistant (PDA) and so on. The LCD comprises a data driver, a scandriver and an LCD panel. The LCD panel has a pixel array. The scandriver sequentially turns on corresponding pixel rows of the pixelarrays so as to scan the pixel data outputted by the data driver to thepixels for displaying an image.

According to most of current technologies, the scan driver capable ofsequentially turning on corresponding pixel rows of a pixel array isembodied by a shift register. As the double-sided scan drivereffectively reduces the bezel area of LCD panel, how to develop a shiftregister having the advantages of being applicable to double-sided scandriver and having a longer lifespan but lighter scan signal distortionhas become an important issue to the manufacturers.

SUMMARY OF THE INVENTION

The invention is directed to a shift register applicable to adouble-sided scan driver and having the advantages of longer lifespanand lighter distortion in scan signals.

According to a first aspect of the present invention, a shift registerused in a double-sided scan driver is provided. The shift registercomprises many stages, and each stage comprises a first, a second, athird level control unit, and a first and a second driving unit. Thefirst level control unit provides a first clock signal to an outputterminal. The first driving unit is coupled to an input terminal of thefirst level control unit via a first node, the voltage in the first nodeis a first control signal. The first driving unit turns on the firstlevel control unit in response to the front edge of an input signal andturns off the first level control unit when the level of the firstcontrol signal of the next stage is higher than the level of the secondcontrol signal. The second level control unit provides a first voltageto an output terminal. The second driving unit turns off the secondlevel control unit in response to the front edge of the first controlsignal and turns on the second level control unit in response to therear edge of the first control signal. The third level control unitprovides a first voltage to an output terminal when the level of thefirst control signal is higher than the level of the second controlsignal. When both the signal at the output terminal and the firstcontrol signal are at high levels, the second control signal is also ata high level.

The invention will become apparent from the following detaileddescription of the preferred but non-limiting embodiments. The followingdescription is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an LCD of a shift register according to afirst embodiment of the invention;

FIG. 2 is a detailed circuit diagram of a stage S(1) of FIG. 1;

FIG. 3 is a related signal clock diagram of the stage S(1) of FIG. 1;

FIG. 4 is a block diagram of an LCD of a shift register according to asecond embodiment of the invention;

FIG. 5 is a detailed circuit diagram of a stage T(1) of FIG. 4;

FIG. 6 is another detailed circuit diagram of the stage T(1) of FIG. 4;

FIG. 7 is a block diagram of an LCD of a shift register according to athird embodiment of the invention;

FIG. 8 is a detailed circuit diagram of a stage U(1) of FIG. 7; and

FIG. 9 is a related signal clock diagram of the stage U(1) of FIG. 7.

FIG. 10 is a block diagram of an LCD of a shift register according to afourth embodiment of the invention.

FIG. 11 is a detailed circuit diagram of a stage W(1) shown in FIG. 10.

FIG. 12 is a related signal clock diagram of the stage W(1) of FIG.

FIG. 13 is another detailed circuit diagram of a stage W(1) shown inFIG. 10.

FIG. 14 is another detailed circuit diagram of a stage W(1) shown inFIG. 10.

FIG. 15 a related signal clock diagram of the stage W(1) of FIG. 12

DETAILED DESCRIPTION OF THE INVENTION First Embodiment

Referring to FIG. 1, a block diagram of an LCD of a shift registeraccording to a first embodiment of the invention is shown. The LCD 10comprises a data driver 12, a scan driver 14 and an LCD panel 16. TheLCD panel 16 comprises a pixel array 18 whose dimension is m×n forexample, wherein both n and m are a natural number larger than 1.

The data driver 12 provides m data signals SD(1)˜SD(m) to the pixelarray 18 via a data line 11. The scan driver 14 is exemplified by adouble-sided scan driver comprising shift registers 14 a and 14 b. Theshift registers 14 a and 14 b located on two sides of the LCD panel 16respectively provides the scan signals of odd-numbered rows of the scansignals SG(1)˜SG(n) and the scan signals of even-numbered rows of thescan signals SG(1)˜SG(n) to the pixel array 18 via the scan lines 13 and13′.

The shift registers 14 a and 14 b respectively comprises multiple stagesof shift register S(1)˜S(k) and stages of shift register S′(1)˜S′(k),wherein the structures of the stages S(1)˜S(k) is identical to that ofthe stages S′(1)˜S′(k). The circuit structures of the stages S(1)˜S(k)are exemplified below, wherein k is a natural number. The stagesS(1)˜S(k) are serially connected and are respectively used to producethe scan signals SG(1), SG(3), SG(5), . . . SG(n-1) of odd-numbered rowsto drive the pixels in the odd-numbered rows of the n rows of the pixelarray 18. From the perspective of the stages S(1)-S(k), S(2) is the nextstage of the S(1) and outputs scan signal SG(3), S(3) is the next stageof S(2) and outputs scan signal SG(5).

On the other hand, S′(2) is the next stage of the S′(1) and outputs scansignal SG(2), S′(3) is the next stage of S′(2) and outputs scan signalSG(4) from the perspective of the stages S′(1)-S′(k). In other words,odd-number stages S(1)-S(k) provide scan signals SG(1), SG(3), SG(5) . .. and even-number stages S′(1)-S′(k) provide scan signals SG(2), SG(4),SG(6) . . . for LCD panel 10.

Each of the stages S(1)˜S(k) comprises an input terminal IN, an outputterminal OUT, a control terminal RT and a clock terminal C. The inputterminal IN of the stage S(1) receives an initial signal STV. The inputterminals IN of the stages S(2)˜S(k) sequentially receive the scansignals

SG(1)˜SG(n-2) outputted from the output terminal OUT of previous stageshift register. Of the stages S(1)˜S(k), the clock terminals C of theodd-numbered stage shift registers units and the clock terminals C ofthe even-numbered stage stages respectively receive a clock signal CK1and a clock signal CK3. The control terminals RT of the stagesS(1)˜S(k-1) respectively receive the control signals VC1(2)˜VC1(K) atthe node P1 of the stages S(2)˜S(k).

The operation of the stage S(1) in response to the clock signal CK1 andthe initial signal STV is disclosed below. Referring to FIG. 2, adetailed circuit diagram of a stage S(1) of FIG. 1 is shown. The stageS(1) comprises two driving units 202 a and 202 b and three level controlunits 204 a, 204 b and 204 c. The driving unit 202 a comprisestransistors T1, T3 and T8. The driving unit 202 b comprises transistorsT4 and T5. The level control units 204 a, 204 b and 204 c respectivelycomprise transistors T2, T7 and T6. In the present embodiment of theinvention, the transistors T1˜T8 are all exemplified by an N-type thinfilm transistor (TFT).

The drain of the transistor T6 is coupled to an output terminal OUT. Thegate receives the control signal VC1(2) of the next stage stage S(2).The source receives a control signal C1. The transistor T6 is turned onfor providing the control signal C1 to the output terminal OUT inresponse to the rising edge of the control signal VC1(2).

The drain of the transistor T3 is coupled to the node P1. The gatereceives the control signal VC1(2). The source receives the controlsignal C1. The transistor T3 provides the control signal C1 to the nodeP1 in response to the rising edge of the control signal VC1(2). In thepresent embodiment of the invention, the control signal C1 is equal tothe clock signal CK1.

The drain of the transistor T1 receives a voltage VDD. The gate iscoupled to the input terminal IN to receive an initial signal STV (thegate of T1 receives the input signal SG(1) in stage S(2), receives theinput signal SG(3) in stage S(3), and receives the input signal SG(5) instage S(4) . . . ). The source is coupled to the node P1. The transistorT1 turns the transistor T2 on in response to the rising edge of theinitial signal STV, so that the scan signal SG(1) is equal to thevoltage VDD.

The drain of the transistor T8 is coupled to the node P1. The gate iscoupled to a node P2 to receive the control signal VC2(1). The sourcereceives a voltage VSS. The transistor T8 provides the voltage VSS tothe node P1 in response to the rising edge of the control signal VC2(1).

The drain of the transistor T2 receives the clock signal CK1. The gateand the source of the transistor T1 together with the drain of thetransistor T3 are coupled to the node P1 to receive the control signalVC1(1). The source is coupled to the output terminal OUT. The transistorT2 is turned on to provides a clock signal CK1, which is at high voltagelevel, to the output terminal OUT.

The drain of the transistor T7 is coupled to the output terminal OUT.The gate is coupled to the source of the transistor T1 and the drain ofthe transistor T3 via the node P2 to receive the control signal VC2(1).The source receives the voltage VSS. The transistor T7 provides thevoltage VSS to the output terminal OUT when the transistor T7 is turnedon.

In the transistor T4, the drain and the gate are coupled together toreceive the voltage VDD. The source is coupled to the node P2. Thesource of the transistor T5 receives the voltage VSS. The gate receivesthe control signal VC1(1). In the present embodiment of the invention,the width/length ratio of the transistor T5 is larger than thewidth/length ratio of the transistor T4. The transistors T4 and T5 forma bias voltage unit, which controls the control signal VC2(1) at a lowlevel to turn off the transistor T7 in response to the high level of thecontrol signal VC1(1) and controls the control signal VC2(1) at a highlevel to turn on the transistor T7 in response to the control signalVC1(1).

Referring to FIG. 3, a related signal clock diagram of the stage S(1) ofFIG. 1 is shown. During the time period TP1, the initial signal STV isequal to the voltage VDD, and the clock signal CK1 and the controlsignal VC1(2) are equal to the voltage VSS. The voltage VDD and thevoltage VSS respectively are the highest voltage level and the lowestvoltage level of the shift register 14 a. Meanwhile, the transistor T1is turned on to make the control signal VC1(1) equal to the high levelVDD−Vth1 so that the transistor T2 is turned on and that the scan signalSG(1) is equal to the clock signal CK1, that is, the voltage VSS. Thetransistors T4 and T5 form an inverter, which makes the control signalVC2(1) equal to the voltage VSS and turns off the transistor T8 and T7in response to the high level of the control signal VC1(1). Thetransistors T3 and T6 are turned off when the gate/source voltage issmaller than 0.

During the time period TP2, the transistors T1, T7 and T8 are turnedoff, and the clock signal CK1 is pulled up from the voltage VSS to thevoltage VDD. Meanwhile, due to the boot-strapping effect, the controlsignal VC1(1) is further pulled up to VC1(1)=VDD−Vth1+ΔV. In the presentembodiment of the invention, the voltage difference ΔV is expressed as:

${{\Delta \; V} = {\frac{C_{gs}}{C_{p\; 1} + C_{gs}}\left( {{VDD} - {VSS}} \right)}},$

wherein Cgs is a parasitic capacitor inside the transistor T2, Cp1 is anequivalent capacitor viewed from the node P1, at which the source of thetransistor T1 couples to the drain of the transistor T8. The controlsignal VC1(1) turns on the transistor T2 to make the scan signal SG(1)quickly charged to the voltage VDD.

The scan signal SG(1) is further outputted to the input terminal IN ofthe stage S(2), so that the control signal VC1(2) of the stage S(2) ispulled up to a high level VDD−Vth1. Meanwhile, the clock signal CK1,that is, the control signal C1, is equal to the voltage VDD, so thatboth the gate-source voltages of the transistors T3 and T6 are smallerthan 0 and both the transistor T3 and T6 are turned off accordingly.

During the time period TP3, the control signal C1 is discharged to thevoltage VSS from the voltage VDD. As the level of the control signalVC1(2) is higher than the level of the control signal C1, thetransistors T3 and T6 are turned on so that the control signal VC1(1)and the scan signal SG(1) are discharged to the voltage VSS. Meanwhile,the transistor T4 and T5, in response to the low level of the controlsignal VC1(1), makes the control signal VC2(1) equal to the voltage VDDto turn on the transistor T7 so that the scan signal SG(1) is equal tothe voltage VSS.

The operation of the stages S(2)˜S(k) differs from that of the stageS(1) in the signal received at the input terminal IN. To be morespecific, the scan signals SG(1)˜SG(k-1) are pulled up to the voltageVDD two time periods earlier than the corresponding clock signals CK1and CK3. Thus, the level of the control signals VC1(2)˜VC1(k) aremaintained at the high level VDD−Vth1 for two time periods and then arepulled up to the high level VDD−Vth1+ΔV. For example, during the timeperiods TP2 and TP3, the control signal VC1(2) of the stage S(2) isequal to the level VDD−Vth1; during the time period TP4, the clocksignal CK3 is pulled up to the voltage VDD from the voltage VSS, so thatthe control signal VC1(2) is pulled up to the high level VDD−Vth1+ΔV.

Thus, the stage S(1) of the present embodiment of the invention providesthe scan signal SG(1) in response to the clock signal CK and the initialsignal STV and so does the subsequent stage S(2) provide the scan signalSG(3) in response to the clock signal CK3 and the scan signal SG(1).Despite the present embodiment of the invention is exemplified by theoperation of the stages S(1) and S(2), the operation of the remainingstages S(3)˜S(k) of the shift register 14 a can also be obtainedaccording to the operation of the stages S(1) and S(2).

The operation of the stages S′(1)˜S′(k) of the shift register 14 bdiffers with the operation of the stage S(1)˜S(k) in the wave pattern ofthe received initial signal STV′ and that the clock signals CK2 and CK4are one time period later than the initial signal STV and the clocksignals CK1 and CK3 respectively. Thus, the stages S′(1)˜S′(k) canexecute the operation similar to that of the stages S(1)˜S(k) to producethe scan signals SG(2), SG(4), . . . , SG(n).

The shift register of the present embodiment of the invention producesthe control signals VC1(1)˜VC1(k) through the circuit of the stages tocontrol the operation of the previous stage by the control signalsVC1(1)˜VC1(k) rather than by the corresponding scan signal. Thus, theshift register of the present embodiment of the invention has theadvantage of shorter delay in the scan signal.

Besides, each stages of the shift register 14 a and 14 b of the presentembodiment of the invention has two control units 204 b and 204 crespectively having a transistor T7 and a transistor T6 for pulling downthe level of the scan signal. When the operation of one of thetransistors T6 and T7 gradually becomes abnormal due to stress effectafter the transistor is turned on for a long time, each stages of thepresent embodiment of the invention can pull down the scan signal to thelowest voltage level through the assistance of another transistor. Thus,each stage of the present embodiment of the invention prevents the scansignal from having erroneous level when the level control unit operatesabnormally, hence having a longer lifespan.

Second Embodiment

Referring to FIG. 4, a block diagram of an LCD of a shift registeraccording to a second embodiment of the invention is shown. On the partof the shift registers 14 a′ and 14 b′ of the present embodiment of theinvention, the stages T(1)˜T(k) and T′(1)˜T′(k) differ with the stagesS(1)˜S(k) and S′(1)˜S′(k) of the first embodiment in that each stageshas two clock terminals C and C′ to receive two of the clock signalsCK1˜CK4 to produce the corresponding scan signals SG(1)˜SG(n). Thefollowing disclosure is exemplified by the stage T(1), and the operationof the stages T(1)˜T(k) and T′(1)˜T′(k) of the present embodiment of theinvention can be obtained according to the operation of the stage T(1).

Referring to FIG. 5, a detailed circuit diagram of a stage T(1) of FIG.4 is shown. The stage T(1) differs with the stage S(1) of the firstembodiment in that the stage T(1) further comprises a transistor T9. Thedrain of the transistor T9 receives a voltage VDD, the gate receives aclock signal CK3, and the source is coupled to a node P2. The transistorT9 provides the voltage VDD to the node P2 in response to the high levelof the clock signal CK3 to make the control signal VC2(1) at the node P2equal to the voltage VDD. The width/length ratio of the transistor T9 issmaller than that of the transistor T5. Thus, when both the transistorT5 and T9 are turned on, the control signal VC2(1) is pulled down to thevoltage VSS by the transistor T5.

During the time periods TP1˜TP3, the clock signal CK3 is equal to thevoltage VSS, and the transistor T9 is turned off. During the time periodTP4, the clock signal CK3 is equal to the voltage VDD. Meanwhile, thetransistor T9 is turned on and the transistor T5 is turned off to makethe control signal VC2(1) equal to the voltage VDD−Vth.

The stages T(1)˜T(k) and T′(1)˜T′(k) of the present embodiment of theinvention differs with the corresponding stages of the first embodimentin that the level control unit 202 b′ has a transistor T9 for making thelevel of the voltage signal VC2(n) equal to VDD−Vth during the timeperiod TP4. Thus, the stage of the present embodiment of the inventionhas the advantages of being applicable to double-sided scan driver andhaving lower load but longer lifespan.

In the present embodiment of the invention, the stages T(1)˜T(k) andT′(1)˜T′(k) all have the circuit structure of FIG. 5 to embody the shiftregister 10′. However, the structures of the stages T(1)˜T(k) andT′(1)˜T′(k) of the present embodiment of the invention are not limitedto the above circuit structure. For example, the stages T(1)˜T(k) andT′(1)˜T′(k) can have a circuit structure as shown in FIG. 6. FIG. 6shows another detailed circuit diagram of the stage T(1) of FIG. 4. Thestage T″(1) differs with the stage T(1) in that the stage T″(1) furthercomprises a level control unit 204 d comprising a transistor T11 andthat the driving unit 202 a′ further comprises a transistor T10.

The drain of the transistor T10 is coupled to the node P1. The gatereceives the clock signal CK3. The source receives the initial signalSTV. The transistor T8 turns on to provide the initial signal STV to thenode P1 in response to a high level of the clock signal CK3. The drainof the transistor T11 is coupled to the output terminal OUT. The gatereceives the clock signal CK3. The source receives the voltage VSS. Thetransistor T11, in response to a high level of clock signal CK3,provides the voltage VSS to the output terminal OUT to make the scansignal SG(1) equal to the voltage VSS.

During the time periods TP1˜TP3, the clock signal CK3 is equal to thelow level VSS; meanwhile, the transistors T10 and T11 are all turnedoff. During the time period TP4, the clock signal CK3 is equal to thehigh level VDD; meanwhile, the transistors T10 and T11 are turned on andrespectively provides the initial signals STV and voltage VSS to thenode P1 and the output terminal OUT. During the time period TP4, theinitial signal STV is equal to the voltage VSS. Thus, the stagesT″(1)˜T″(k) of the present embodiment of the invention also have theadvantages of being applicable to double-sided scan driver and havinglower load but longer lifespan.

Third Embodiment

Referring to FIG. 7 and FIG. 8. FIG. 7 is a block diagram of an LCD of ashift register according to a third embodiment of the invention. FIG. 8is a detailed circuit diagram of a stage U(1) shown in FIG. 7. The LCD10″ of the present embodiment of the invention differs with the LCD 10′of the second embodiment in that the shift register 14″ employs threeclock signals CK1′, CK2′ and CK3′ and that the transistors T9, T10 andT11 of the stage T″(1) are respectively replaced by the transistors T9′,T10′ and T11′of the stage U(1). The transistors T9′, T10′ and T11′differ with the corresponding transistors T9 and T10 and T11 in that thegate of each of the transistors T9′, T10′ and T11′ receives a clocksignal CK2′.

Referring to FIG. 9, a related signal clock diagram of the stage U(1) ofFIG. 7 is shown. The stage U(1) of the present embodiment of theinvention differs and the stages S(1), T(1) and T″(1) of the first andthe second embodiment are the same in having a similar clock wavepattern but are different in that the clock signal CK2′ is pulled up toa high level one time period earlier than the clock signal CK3. Thus,during the time period TP3, the transistors T9′, T10′ and T11′ caneffectively make the control signal VC2(1) equal to the voltage VDD,make the control signal VC1(1) equal to the voltage VSS, and make thescan signal SG(1) equal to the voltage VSS. Thus, the stages U(1)˜U(k)and U′(1)˜U′(k) of the present embodiment of the invention also have theadvantages of being applicable to double-sided scan driver and havinglower load but longer lifespan.

Fourth Embodiment

Referring to FIG. 10, a block diagram of an LCD of a shift registeraccording to a fourth embodiment of the invention is shown. The LCD 20of the present embodiment of the invention is different from the LCD 10of the first embodiment in that each of the stages W(1)-W(k) andW′(1)-W′(k) has two control terminals RT1 and RT2. The control terminalRT2, as substantially the same as the control terminal RT in FIG. 1,receives control signal VC1 of the succession stage. The controlterminal RT1 receives the scan signal SG of the succession stage. Fromthe perspective of the stages W(1)-W(k), W(2) is the next stage of theW(1) and outputs scan signal SG(3), W(3) is the next stage of W(2) andoutputs scan signal SG(5). On the other hand, W′(2) is the next stage ofthe W′(1) and outputs scan signal SG(2), W′(3) is the next stage ofW′(2) and outputs scan signal SG(4) from the perspective of the stagesW′(1)-W′(k). In other words, odd-number stages W(1)-W(k) provide scansignals SG(1), SG(3), SG(5) . . . and even-number stages W′(1)-W′(k)provide scan signals SG(2), SG(4), SG(6) . . . for LCD panel 26.

Referring to FIG. 11, a detailed circuit diagram of a stage W(1) shownin FIG. 10 is shown. Instead of including the transistor T3, the drivingcircuit 402 a includes a transistor T3′. The gate receives the scansignal SG(3) from next stage W(2). The source receives the voltage VSS.The driving circuit 402 a further includes a transistor T10. The gatereceives the clock signal CK3. The source receives the initial signalSTV (the source receives the input signal SG(1) in stage W(2), receivesthe input signal SG(3) in stage W(3), and receives the input signalSG(5) in stage W(4) . . . ). The drain is coupled to the node P1.Likewise, the transistor T3′ in stage W(2) receives the scan signalSG(5) from next stage W(3) to turn on or turn off the level control unit404 a.

Instead of including the transistor T4 and T5, the driving circuit 402 bincludes transistors T5, T12, T13 and a capacitor C′. Besides the levelcontrol units 404 a, 404 b, and 404 c, which have substantially the samecircuit structures as the level control units 204 a, 204 b, and 204 c,the stage W(1) further comprises level controller 404 d, which includesa transistor T11. The gate receives the clock signal CK3. The sourcereceives the voltage VSS. The drain is coupled to the output terminalOUT.

Referring to FIG. 12, a related signal clock diagram of the stage W(1)of FIG. 11 is shown. Since the transistor T3 is replaced by thetransistor T3′ in the present embodiment, the voltage level of thecontrol signal VC1(1) is pulled down from the voltage VDD−Vth to thevoltage VSS in the time period TP4′. Similarly, the transistor T10 isalso enabled in the time period TP4′ for pulling down the control signalVC1(1) from the voltage VDD−Vth to the voltage VSS.

The transistors T5, T12, T13, and the capacitor C′ forms a voltageregulator for lifting the voltage level of the control signal VC2(1) atnode P2 to the voltage VDD−Vth when the driving unit 402 a provide thevoltage VSS from the node P1 to the driving unit 402 b at the beginningof a time period TP′4.

The transistor T11 is enabled at the beginning of the time period TP4′for pulling down the scan signal SG(1) from the voltage VDD to thevoltage VSS. Thus, the stages W(1)˜W(k) and W′(1)˜W′(k) of the presentembodiment of the invention also have the advantages of being applicableto double-sided scan driver and having lower load but longer lifespan.

Referring to FIG. 13, another detailed circuit diagram of a stage W(1)shown in FIG. 10 is shown. The stage X(1) is different from the stageW(1) shown in FIG. 11 in that the driving unit 402 b′ further includestransistor T14. The gate receives the input signal STV (the gatereceives the input signal SG(1) in stage W(2), receives the input signalSG(3) in stage W(3), and receives the input signal SG(5) in stage W(4) .. . ). The source receives the voltage VSS. The drain is coupled to thenode P2. Referring to FIG. 12, it can be obtained that the transistorT14 is turned on for pulling the control signal VC2(1) down to thevoltage VSS in the time period TP1.

Referring to FIG. 14, another detailed circuit diagram of a stage W(1)shown in FIG. 10 is shown. The stage Y(1) is different from the stageW(1) in that the driving unit 402 b is replaced by a driving unit 402b′, which includes transistors T4′, T5′, T14′, and T15. The operationsand circuit connections of the transistors T4′ and T5′ are substantiallythe same as that of the transistor T4 and T5 shown in FIG. 2 forinverting the control signal VC1(1) to accordingly obtain the controlsignal VC2(1). The operation of the transistor T14′ is substantially thesame as the transistor T14 for pulling the control signal VC2(1) down tothe voltage VSS in the time period TP1.

Referring to FIG. 12, it can be obtained that the transistor T15 isturned on for pulling the control signal VC2(1) up to the voltage VDD inthe time period TP4′. In the present embodiment of the invention, thewidth/length ratio of the transistor T5′ is larger than the width/lengthratio of the transistor T15. Thus, even the transistor T15 is turned onin the time period TP4′, the level of the control signal VC2(1) is keptto be the voltage VSS since the transistor T5′ is turned on. Thus, thestage W(1)-W(K) and W′(1)-W′(k) shown in FIG. 10 can also be implementedwith the stages X(1) and Y(1) respectively shown in FIG. 13 and FIG. 14.

Though only the example that the stage W(1) works with signals shown inthe clock diagram in FIG. 12 is illustrated as an example in the presentembodiment of the invention, the stage W(1) is not limited thereto. Inother example, as shown in FIG. 15, clock signals CK1′ and CK3′ withdoubled duty cycles are applied in the stage W(1). Thus, the duty cyclesof each of the scan signals SG′(1) to SG′(n) are also doubled and theenabled time for each of the scan signals SG′(1) to SG′(n) is partiallyoverlapped with that of the succession scan signal.

For example, the scan signal SG′(2) is enabled in time periods TPP1 andTPP2 for enabling a corresponding row (ex: 2^(nd) row) in the pixelarray 28 and the scan signal SG′(1) is enabled in time periods TPP0 andTPP1 for enabling a corresponding row (ex: 1^(st) row) in the pixelarray 28.

In the time period TPP1, data signals SD(1) to SD(m) corresponding tothe 1^(st) row are provided via the data driver 22. Thus, the enabled mpixels on the 1^(st) row are charged by the respective data signalsSD(1) to SD(m) corresponding to the 1^(st) row for display thecorresponding image in the time period TPP1. Meanwhile, the m pixels onthe 2^(nd) row are also enabled in the time period TTP1. Thus, theenabled m pixels on the 2^(nd) row are precharged by the respective datasignals SD(1) to SD(m) corresponding to the 1^(st) row in the timeperiod TPP1.

In the time period TPP2, data signals SD(1) to SD(m) corresponding tothe 2^(nd) row are provided via the data driver 22. Thus, the enabled mpixels on the 2^(nd) row are charged by the respective data signalsSD(1) to SD(m) corresponding to the 2^(nd) row for display thecorresponding image in the time period TPP2. Similarly, the m pixels onthe 3^(rd) row are also enabled and precharged by the respective datasignals SD(1) to SD(m) corresponding to the 2^(nd) row in the timeperiod TPP2.

In other words, the pixel data signals corresponding to the presentselected pixel row are used to precharge the succession pixel row. Thus,the reaction time of the LCD panel 26 can also be effectively reduced.

In the embodiments of the invention as shown in FIG. 1˜FIG. 15, thecontrol signal CK1 and CK3 interchange between adjacent stages. Forexample, referring to FIG. 10 and FIG. 11, control signal (clock signal)CK1 is inputted to transistor T2, T6 and CK3 is inputted to transistorT10, T11 in stage W(1). However, control signal (clock signal) CK1 isinputted to transistor T10, T11 and CK3 is inputted to transistor T2, T6in stage W(2). Likewise, control signal (clock signal) CK2 is inputtedto transistor T2, T6 and CK4 is inputted to transistor T10, T11 in stageW′(1). Control signal (clock signal) CK1 is inputted to transistor T10,T11 and CK3 is inputted to transistor T2, T6 in stage W′(2). In FIG.1˜FIG. 13, each of the clock signals CK1˜CL4 or CK′1˜CK′4 is at highlevel voltage during a quarter period and is at low level voltage duringthree quarter period. As a result, the clock signal CK3 (CK′3) isdelayed by a two quarter period with respect to the clock signalCK1(CK′1). The clock signal CK4 (CK′4) is delayed by a two quarterperiod with respect to the clock signal CK2(CK′2). In FIG. 14˜FIG. 15,the clock signal CK′3 is in opposite phase with respect to the clocksignal CK′1, and clock signal CK′4 is in opposite phase with respect tothe clock signal CK′2.

While the invention has been described by way of example and in terms ofa preferred embodiment, it is to be understood that the invention is notlimited thereto. On the contrary, it is intended to cover variousmodifications and similar arrangements and procedures, and the scope ofthe appended claims therefore should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements and procedures.

1. A shift register having a plurality of stages provided on two sidesof a display panel for providing scan signals , wherein each stage ofthe shift register on one side of the display panel comprises: a firstlevel control unit for providing a first clock signal to an outputterminal; a first driving unit coupled to an input terminal of the firstlevel control unit via a first node for providing a first controlsignal, wherein the first driving unit turns on the first level controlunit in response to a front edge of an input signal and turns off thefirst level control unit when the level of the first control signal ofthe next stage is higher than the level of a second control signal thatis input to the first level control unit; a second level control unitfor providing a first voltage to the output terminal; a second drivingunit for turning off the second level control unit in response to thefront edge of the first control signal and turning on the second levelcontrol unit in response to the rear edge of the first control signal;and a third level control unit for providing the first voltage to theoutput terminal when the level of the first control signal of the nextstage is higher than the level of the second control signal that isinput to the third level control unit, wherein: when both the signal atthe output terminal and the first control signal are at high levels, thesecond control signal is also at a high level.
 2. The shift registeraccording to claim 1, wherein the third level control unit comprises: afirst transistor, wherein the gate receives the first control signal ofthe next stage, the first source/drain is coupled to the outputterminal, and the second source/drain receives the second control signalthat is equal to the first clock signal.
 3. The shift register accordingto claim 2, wherein the first driving unit comprises: a thirdtransistor, wherein the gate receives the first control signal of thenext stage, the first source/drain is coupled to the first node, and thesecond source/drain receives the second control signal.
 4. The shiftregister according to claim 3, wherein the first driving unit furthercomprises: a fifth transistor, wherein the gate receives the inputsignal, the first source/drain receives a second voltage, and the secondsource/drain is coupled to the first node.
 5. The shift registeraccording to claim 3, wherein the first driving unit further comprises:a fourth transistor, wherein the gate is coupled to the second drivingunit via a second node for receiving a third control signal, the firstsource/drain is coupled to the first node, and the second source/drainreceives the first voltage.
 6. The shift register according to claim 3,wherein the first driving unit further comprises: a fifth transistor,wherein the gate receives a second clock signal, the first source/drainis coupled to the first node, the second source/drain receives the inputsignal, the fifth transistor provides the input signal to the first nodewhen the level of the second clock signal is higher than the inputsignal; wherein the enabling time of the second clock signal and theenabling time of the first clock signal are non-overlapped, and thesecond clock signal is delayed by a two quarter period with respect tothe first clock signal.
 7. The shift register according to claim 1,wherein the second driving unit comprises: a bias voltage unit coupledto the input terminal of the second level control unit via the secondnode for providing the third control signal, wherein the bias voltageunit pulls down the level of the third control signal to turn off thesecond level control unit in response to the front edge of the firstcontrol signal and pulls up the level of the third control signal toturn on the second level control unit in response to the rear edge ofthe first control signal.
 8. The shift register according to claim 7,wherein the second driving unit further comprises: a sixth transistor,wherein the gate receives a second clock signal, the first source/drainreceives a second voltage, and the second source/drain is coupled to thesecond node.
 9. The shift register according to claim 7, wherein thesecond level control unit comprises: a ninth transistor, wherein thegate receives the third control signal, the first source/drain iscoupled to the output terminal, and the second source/drain receives thefirst voltage.
 10. The shift register according to claim 9, whereinfurther comprises: a fourth level control unit comprising a secondtransistor, wherein the gate receives a second clock signal, the firstsource/drain is coupled to the output terminal, the second source/drainreceives the first voltage, the second transistor provides the firstvoltage to the output terminal in response to a rising edge of thesecond clock signal; wherein the enabling time of the second clocksignal and of the first clock signal the enabling time arenon-overlapped.
 11. The shift register according to claim 1, wherein thefirst level control unit comprises: a seventh transistor, wherein thegate receives the first control signal, the first source/drain receivesthe first clock signal, and the second source/drain is coupled to theoutput terminal.
 12. The shift register according to claim 1, wherein afirst stage among the stages receives an initial signal used as theinput signal.
 13. The shift register according to claim 1, wherein theenabling times of the first clock signals received by any two adjacentstages are non-overlapped, and a first clock signal received by nextstage is delayed by a two quarter period with respect to the first clocksignal.